Memory circuit and method of forming the same using reduced mask steps

ABSTRACT

Disclosed is a memory circuit and method of forming the same. The memory circuit comprises a lower metallization layer defining first conducting lines. A continuous magnetic storage element stack is atop the lower metallization layer wherein a bottom electrode of the stack is in direct contact with the first conducting lines. An upper metallization layer is atop the continuous magnetic storage element stack, the upper metallization layer defining second conducting lines, which are in direct contact with said continuous magnetic storage element stack. Localized areas of the continuous magnetic storage element stack define discrete magnetic bits, each energizable through a selected pair of the first and second conducting lines. In a second aspect and a third aspect, the continuous magnetic storage element stack is respectively partially and fully etched through a single mask, to define the discrete magnetic bits.

FIELD

Embodiments of the invention relate to a memory circuit using magneticstorage elements and particularly relate to magnetic random accessmemory (MRAM) circuits.

BACKGROUND

Magnetic (or magneto-resistive) random access memory (MRAM) circuitshave several desirable characteristics such as high speed, high density(i.e., small bit cell size), low power consumption, and no degradationover time, particularly over the dynamic random access memory (DRAM)circuit. MRAM circuits are integrated typically with a complementarymetal-oxide semiconductor (CMOS) technology.

FIG. 1A illustrates a section of an exemplary layout for an MRAM circuit100A, that includes a set of first conducting lines 118 to form wordlines and a set of second conducting lines 102 to form bit lines. Theset of second conducting lines 102 overlies the set of first conductinglines 118 to define crossover zones 103. Addressable magnetic storageelement stacks 122 are disposed within the crossover zones 103. Currentdrivers 101 are provided for energizing the first conducting lines 118and the second conducting lines 102. Each of the magnetic storageelement stacks 122 correspond to a bit cell in the MRAM circuit 100A,and is isolated from other magnetic storage element stacks 122.

FIG. 16 illustrates a cross sectional view of two adjacent magneticstorage element stacks 122 between the first conducting line 118 and thesecond conducting line 102, in the region marked ‘X’ in FIG. 1A, In FIG.16, an access transistor 124 is also shown schematically, correspondingto each of the two magnetic storage element stacks 122, to represent twobit cells A and B. The magnetic storage element stacks 122 are designedto be integrated into a back-end metallization structure following afront-end CMOS processing. In a bit cell, the magnetic storage elementstack 122 includes a structure having two ferromagnetic layers which arereferred to as a ‘fixed layer’ 110 and a ‘free layer’ 106. The twolayers 110,106, are separated by a non-magnetic barrier layer that isreferred to as ‘a tunnel oxide layer’ 108. All the three layers alongwith an extended bottom electrode 112 are arranged to form a magnetictunnel junction (MTJ) stack 122. The free layer 106 is connected to anupper metallization layer through an upper interface via hole 104. Thebottom electrode 112 is connected to a lower metallization layer,through a lower interface via hole 116. The upper metallization layer ispatterned to include the bit lines corresponding to each MTJ stack 122.The lower metallization layer is patterned to include a write word line118 c and a read word line 118 b, for reading and writing operationsfrom and into each MTJ stack 122. A connection 118 a between the lowermetallization layer and a corresponding access transistor 124 for thereading operation in a bit cell, is also shown. The write word line 118c for the writing operation in a bit cell has no contact with the bottomelectrode 112, and when energized, induces a magnetic field at ajunction of the MTJ stack 122. The upper and lower metallization layersare shown to be an M3 layer and an M2 layer respectively, Forfabricating this structure with the MTJ stack 122, after patterning theM2 layer and before forming the M3 layer, four masking and etching stepsare likely to be required, such as: a) lower interface via mask and etchfor defining the lower interface via hole 116, in order to connect theindividual bottom electrodes 112 to the lower metallization layer, b)bottom electrode mask and etch for defining the individual bottomelectrodes 112, c) magnetic stack etch mask and etch for defining theindividual MTJ stacks 122 up to the bottom electrode 112, and d) upperinterface via mask and etch for defining the upper interface via hole104, in order to connect the free layers 106 to the upper metallizationlayer. The fully isolated individual magnetic storage element stacks 122are encapsulated by dielectric regions 120. Smaller the area of the MTJstack 122, better is the efficiency of the writing operation. For eachof the bit cells A and B, the bottom electrode 112 extends beyond thearea of the free layer 106, the tunnel oxide layer 108 and the fixedlayer 110, and accommodates the corresponding write word line 118 c andthe corresponding read lines 118 a,b.

SUMMARY OF THE INVENTION

A first aspect of the invention provides a memory circuit. A lowermetallization layer defines first conducting lines. A continuousmagnetic storage element stack is over the lower metallization layer anda bottom electrode of the stack is in direct contact with the firstconducting lines. An upper metallization layer is over the continuousmagnetic storage element stack. The upper metallization layer definessecond conducting lines, which are in direct contact with the continuousmagnetic storage element stack. Localized areas of the continuousmagnetic storage element stack define discrete magnetic bits, eachenergizable through a selected pair of the first and second conductinglines.

A second aspect of the invention provides a memory circuit. A lowermetallization layer defines first conducting lines. A magnetic tunneljunction (MTJ) stack is over the patterned lower metallization layer anda bottom electrode of the stack is in direct contact with the firstconducting lines. The stack has a top free layer, a middle tunnel oxidelayer and a bottom fixed layer overlying the bottom electrode. The stackis patterned through a single mask, by etching the top free layer untilthe tunnel oxide layer, to define partially isolated individual stacks.An upper metallization layer is over the partially isolated individualstacks and defines second conducting lines, which are in direct contactwith the partially isolated individual stacks. The partially isolatedindividual stacks are encapsulated by dielectric regions and definediscrete magnetic bits, each energizable through a selected pair of thefirst and second conducting lines.

A third aspect of the invention provides a memory circuit. A lowermetallization layer defines first conducting lines. A magnetic tunneljunction (MTJ) stack is over the patterned lower metallization layer anda bottom electrode of the stack is in direct contact with the firstconducting lines. The stack has a top free layer, a middle tunnel oxidelayer and a bottom fixed layer overlying the bottom electrode. The stackis patterned by etching through a single mask, to define fully isolatedindividual stacks. An upper metallization layer is over the fullyisolated individual stacks to define second conducting lines, which arein direct contact with said fully isolated individual stacks. The fullyisolated individual stacks are encapsulating by dielectric regions anddefine discrete magnetic bits, each energizable through a selected pairof the first and second conducting lines.

A fourth aspect of the invention provides a method for forming a memorycircuit. The method includes the steps of patterning a lowermetallization layer to define first conducting lines, followed byforming a continuous magnetic storage element stack over the patternedlower metallization layer, such that a bottom electrode of the stack isin direct contact with the first conducting lines. This is followed byforming an upper metallization layer over the continuous magneticstorage element stack and then by patterning the upper metallizationlayer to define second conducting lines, which are in direct contactwith said continuous magnetic storage element stack. Localized areas ofthe continuous magnetic storage element stack define discrete magneticbits, each energizable through a selected pair of the first and secondconducting lines.

According to an embodiment of each of the first and the fourth aspectsof the invention, the magnetic storage element stack has a magnetictunnel junction (MTJ) stack.

A fifth aspect of the invention provides a method for forming a memorycircuit. The method includes the steps of patterning a lowermetallization layer to define first conducting lines, followed byforming a continuous magnetic storage element stack over said patternedlower metallization layer such that a bottom electrode of the stack isin direct contact with the first conducting lines. The stack has a topfree layer, a middle tunnel oxide layer and a bottom fixed layeroverlying the bottom electrode. This is followed by patterning the stackthrough a single mask, by etching the top free layer until the tunneloxide layer, to define partially isolated individual stacks. This isfollowed by forming an upper metallization layer over the partiallyisolated individual stacks and then patterning the upper metallizationlayer to define second conducting lines, which are in direct contactwith the partially isolated individual stacks. The partially isolatedindividual stacks are encapsulated by dielectric regions. The partiallyisolated individual stacks define discrete magnetic bits, eachenergizable through a selected pair of the first and second conductinglines.

A sixth aspect of the invention provides a method for forming a memorycircuit. The method includes the steps of patterning a lowermetallization layer to define first conducting lines, followed byforming a continuous magnetic storage element stack over the patternedlower metallization layer such that a bottom electrode of the stack isin direct contact with the first conducting lines. The stack has a topfree layer, a middle tunnel oxide layer and a bottom fixed layeroverlying the bottom electrode. This is followed by patterning the stackthrough a single mask, by etching to define fully isolated individualstacks, then forming an upper metallization layer over the fullyisolated individual stacks, and then patterning the upper metallizationlayer to define second conducting lines, which are in direct contactwith the fully isolated individual stacks. The fully isolated individualstacks are encapsulated by dielectric regions. The fully isolatedindividual stacks define discrete magnetic bits, each energizablethrough a selected pair of the first and second conducting lines.

According to an embodiment for each of the first to the sixth aspects ofthe invention, the lower metallization layer has an M2 layer and theupper metallization layer has an M3 layer.

According to another embodiment for each of the first to the sixthaspects of the invention, the first conducting lines have a plurality ofword lines and the second conducting lines have a plurality of bitlines.

According to the first and fourth aspects of the invention, the fourmasking and etching steps as described in the foregoing ‘Background’section can be avoided. Similarly, according to the second and fifthaspects of the invention, etching the top free layer until the tunneloxide layer is achieved through only a single mask and a partial etch.According to the third and sixth aspects of the invention, full etchingof the stack is achieved through only a single mask. All these aspectsof the invention and their embodiments enable significant savings in theprocessing time and cost. Reduced number of processing steps alsoenhance yield.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates a section of an exemplary layout for an MRAMcircuit. A set of second conducting lines overlies a set of firstconducting lines to define crossover zones. Addressable magnetic storageelement stacks are disposed within the crossover zones. Each of themagnetic storage element stacks correspond to a bit cell in the MRAMcircuit.

FIG. 1B illustrates a cross sectional view of two adjacent magneticstorage element stacks in the region marked ‘X’ in FIG. 1A. Each stackhas a corresponding access transistoras shown schematically, torepresent two bit cells A and B. The two magnetic storage element stacksare isolated from each other.

FIG. 2 illustrates a view similar to that of FIG. 1B and according to anembodiment of the invention. In this embodiment, the magnetic storageelement stack is continuous between the bit cells A and B, requiring useof reduced masking and etching steps.

FIG. 3 illustrates a view similar to that of FIG. 1B and according to anembodiment of the invention. In this embodiment, the magnetic storageelement stack is patterned through a single mask, to define partiallyisolated individual stacks for the two bit cells A and B.

FIG. 4 illustrates a view similar to that of FIG. 1B and according to anembodiment of the invention. In this embodiment, the magnetic storageelement stack is patterned through a single mask, to define fullyisolated individual stacks for the two bit cells A and B.

DETAILED DESCRIPTION

In the following description, for purposes of explanation, numerousspecific details are set forth in order to provide a thoroughunderstanding of the invention. It will be apparent, however, to oneskilled in the art that the invention can be practiced without thesespecific details.

Reference in this specification to “one embodiment” or “an embodiment”means that a particular feature, structure, or characteristic describedin connection with the embodiment is included in at least one embodimentof the invention. The appearances of the phrase “in one embodiment” invarious places in the specification are not necessarily all referring tothe same embodiment, nor are separate or alternative embodimentsmutually exclusive of other embodiments. Moreover, various features aredescribed which may be exhibited by some embodiments and not by others.Similarly, various requirements are described which may be requirementsfor some embodiments but not other embodiments.

FIG. 2 illustrates a section of an MRAM circuit 200, according to anembodiment of the invention, showing the arrangement for the twoadjacent bit cells A and B. The magnetic storage element stack 222 isdesigned to be integrated into a back-end metallization structurefollowing a front-end CMOS processing. A lower metallization layerdefines the first conducting lines 218 a and 218 b. The continuousmagnetic storage element stack 222 overlies the lower metallizationlayer, such that the bottom electrodes 212 of the stack 222 are indirect contact with the first conducting lines 218 a. The term ‘directcontact’ here indicates that there is no via hole for making the contactand that there may be one or more intermediate conducting layers, asshown by a lower interface layer 216. An upper metallization layeroverlies the continuous magnetic storage element stack 222, the uppermetallization layer defining second conducting lines 202, which are indirect contact with said continuous magnetic storage element stack 222.The term ‘direct contact’ here again indicates that there is no via holefor making the contact and that there may be one or more intermediateconducting layers, as shown by an upper interface layer 204. Localizedareas of said continuous magnetic storage element stack 222 definediscrete magnetic bits 214, each energizable through a selected pairfrom the first conducting lines 218 a, 218 b, 218 c and the secondconducting lines 202, A connection between the lower metallization layerand a corresponding access transistor 224 for the reading operation fromeither bit cell, is also shown. A method of forming the memory circuit200 includes the steps of patterning the lower metallization layer todefine the first conducting lines 218 a, 218 b, followed by forming thecontinuous magnetic storage element stack 222 over said patterned lowermetallization layer, such that the bottom electrodes 212 are in directcontact with the first conducting lines 218 a. This is followed byforming the upper metallization layer over the continuous magneticstorage element stack 222 and then by patterning the upper metallizationlayer to define second conducting lines 202, which are in direct contactwith said continuous magnetic storage element stack 222. With thisembodiment, all the four masking and etching steps a) to d) as describedin the foregoing ‘Background’ section, can be avoided.

FIG. 3 illustrates a section of an MRAM circuit 300, according to anembodiment of the invention, showing the arrangement for the twoadjacent bit cells A and B. The magnetic storage element stack 322 isdesigned to be integrated into a back-end metallization structurefollowing a front-end CMOS processing. A lower metallization layerdefines the first conducting lines 318 a, 318 b, 318 c. A magnetictunnel junction (MTJ) stack 322 is over the patterned lowermetallization layer and the bottom electrodes 312 of the stack 322 arein direct contact with the first conducting lines 318 a. The term‘direct contact’ here indicates that there is no via hole for making thecontact and that there may be one or more intermediate conductinglayers, as shown by a lower interface layer 316. The stack 322 has a topfree layer 306, a middle tunnel oxide layer 308 and a bottom fixed layer310 over the bottom electrode 312. The stack 322 is patterned through asingle mask, by etching the top free layer 306 until the tunnel oxidelayer 308, to define partially isolated individual stacks 322. An uppermetallization layer is over the partially isolated individual stacks 322and defines second conducting lines 302, which are in direct contactwith said partially isolated individual stacks. The term ‘directcontact’ here again indicates that there is no via hole for making thecontact and that there may be one or more intermediate conductinglayers, as shown by an upper interface layer 304. The partially isolatedindividual stacks 322 are encapsulated by dielectric regions 320. Thepartially isolated individual stacks 322 define discrete magnetic bits314, each energizable through a selected pair from the first conductinglines 318 a, 318 b and the second conducting lines 302. A connectionbetween the lower metallization layer and a corresponding accesstransistor 324 for the reading operation from either bit cell, is alsoshown. A method for forming the memory circuit 300 includes the steps ofpatterning the lower metallization layer to define the first conductinglines 318 a, 318 b, followed by forming the continuous magnetic storageelement stack 322 over the patterned lower metallization layer, suchthat the bottom electrodes 312 of the stack 322 are in direct contactwith the first conducting lines 318 a. This is followed by patterningthe stack 322 by etching the top free layer 306 until the tunnel oxidelayer 308 through a single mask, to define partially isolated individualstacks 322. This is followed by forming the upper metallization layerover the partially isolated individual stacks 322 and then patterningthe upper metallization layer to define second conducting lines 302,which are in direct contact with said partially isolated individualstacks 322. The partially isolated individual stacks 322 areencapsulated by dielectric regions 320 before forming the uppermetallization layer or after patterning the upper metallization layer.With this embodiment, the three masking and etching steps as describedat a), b) and d) in the foregoing ‘Background’ section can be avoided.The masking and etching step at c) undergoes a partial etch in thisaspect of the invention.

FIG. 4 illustrates a section of an MRAM circuit 400, according to anembodiment of the invention, showing the arrangement for the twoadjacent bit cells A and B. The magnetic storage element stack 422 isdesigned to be integrated into a back-end metallization structurefollowing a front-end CMOS processing. The memory circuit 400 includes alower metallization layer defining first conducting lines 418 a, 418 b.A magnetic tunnel junction (MTJ) stack 422 is over the patterned lowermetallization layer and the bottom electrodes 412 of the stack 422 arein direct contact with the first conducting lines 418 a. The term‘direct contact’ here indicates that there is no via hole for making thecontact and that there may be one or more intermediate conductinglayers, as shown by a lower interface layer 416. The stack 422 has a topfree layer 406, a middle tunnel oxide layer 408 and a bottom fixed layer410 overlying the bottom electrode 412. The stack 422 is patternedthrough a single mask, by etching, to define fully isolated individualstacks 422. An upper metallization layer is over the fully isolatedindividual stacks 422 defining second conducting lines 402, which are indirect contact with said fully isolated individual stacks 422. The fullyisolated individual stacks 422 are encapsulating by dielectric regions420. The fully isolated individual stacks 422 define discrete magneticbits 414, each energizable through a selected pair from the firstconducting lines 418 a, 418 b and the second conducting lines 402. Aconnection between the lower metallization layer and a correspondingaccess transistor 424 for the reading operation from either bit cell, isalso shown. A method for forming the memory circuit 400 includes thesteps of patterning the lower metallization layer to define the firstconducting lines 418, followed by forming the continuous magneticstorage element stack 422 over the patterned lower metallization layersuch that the bottom electrodes 412 of the stack 422 are in directcontact with the first conducting lines 418 a. This is followed bypatterning the stack 422 through a single mask, by etching the stack422, to define fully isolated individual stacks 422. This is followed byforming the upper metallization layer over the fully isolated individualstacks 422 and then patterning the upper metallization layer to definesecond conducting lines 402, which are in direct contact with said fullyisolated individual stacks 422. The fully isolated individual stacks 422are encapsulated by dielectric regions 420 before forming the uppermetallization layer or after patterning the upper metallization layer.

According to the embodiments shown in FIGS. 2-4, the respective magneticstorage element stack 222, 322, 422 has magnetic tunnel junction (MTJ)stack, while the lower metallization layer has an M2 layer and the uppermetallization layer has an M3 layer. However, any other set ofconsecutive layers in a backend process may equally be used, dependingon the number of metal layers stacked in the back-end process, theconvenience of processing and the attainable performance for therespective memory circuit 200, 300, 400. Also, the first conductinglines 218(a,b), 318(a,b), 418(a,b) include a plurality of word lines andthe second conducting lines 202, 302, 402 include a plurality of bitlines. Only two bit cells A and B are shown, however, the scope of theembodiments of the invention does not limit the numbers of the bitcells. The scope of the embodiments of the invention is also not limitedto any particular technology in terms of processing sequence, materials,physical dimensions and the like.

The embodiments as described in FIGS. 2-4 may however suffer fromdrawbacks in performance of the memory circuits 200,300,400. Thecontinuous magnetic storage element stack 222 remains susceptible tointerference effects between adjacent magnetic bits 214. The partiallyisolated individual stacks 322 also remains susceptible to interferenceeffects between adjacent magnetic bits 314. The partially isolatedindividual stacks 322 have the free layers 306 for the magnetic bits 314isolated from each other by the dielectric region 320, hence theinterference effect is likely to be lesser as compared to the case whenthe continuous magnetic storage element stack 222 is used. The fullyisolated individual stacks 422 have all the four layers (free layer 406,tunnel oxide layer 408, fixed layer 410 and bottom electrode 412) forthe magnetic bits 414 isolated from each other by the dielectric region420, hence the interference effect is likely to be least as compared tothe case when the continuous magnetic storage element stack 222 or thepartially isolated individual stacks 322 is used. As illustrated in FIG.16, the write operation uses a write word line 118 c for inducing amagnetic field at the junction. However, in the embodiments of theinvention illustrated in FIGS. 2-4, since the bottom electrodes 212,312, 412 directly make contact with the lower metallization layer, theinducing action as achievable by the write word line 118 c is notpossible. Hence, the embodiments of the present invention can be usedfor read operations only, unless alternate arrangements are made forwriting operation.

In consideration with the aforesaid limitations, the aspects andembodiments of the present invention embodiments may however be usefulfor applications where maintaining low cost for the memory circuits 200,300, 400 is of higher priority than the quality of performance. One suchapplication may be for memory circuits 200, 300, 400 which are ofdisposable types, which are designed for short term usages and are oflower complexity. The interference effects may be reduced by increasingthe distance between the magnetic bits 214, 314, 414 in the layoutdesign for the memory circuits 200, 300, 400 which would however be atthe cost of increased area. Similarly, the aspects and embodiments ofthe present invention embodiments may be useful for applications whereonly reading operation is required, and not writing operation.

All the aspects of the invention provides a memory circuit, that iscompatible with any semiconductor technology such as complementarymetal-oxide-semiconductor (CMOS), bipolar-junction-transistor and CMOS(BiCMOS), silicon-on-insulator (SOI) and the like. The embodiments ofthe invention are equally applicable when any other type of magneticstorage element stack 222, 322, 422 is used.

Although the present invention has been described with reference tospecific exemplary embodiments, it will be evident that the variousmodification. and changes can be made to these embodiments withoutdeparting from the broader spirit of the invention. Accordingly, thespecification and drawings are to be regarded in an illustrative senserather than in a restrictive sense.

1. (canceled)
 2. (Canceled)
 3. (canceled)
 4. A circuit including a first bit cell and a second bit cell, wherein the circuit comprises: a magnetic tunnel junction (“MTJ”) stack, wherein the MTJ stack includes: a bottom electrode; a fixed layer above the bottom electrode; a free layer above the fixed layer; and a tunnel layer between the fixed layer and the free layer, wherein: the free layer is divided by a dielectric region into a first part in the first bit cell and a second part in the second bit cell; and the fixed layer extends continuously between the first bit cell and the second bit cell.
 5. The circuit of claim 4, further comprising a first metallization layer including a first plurality of conducting lines, wherein the first metallization layer is below the bottom electrode of the MTJ stack.
 6. The circuit of claim 5, further comprising a first interface layer between the first metallization layer and the bottom electrode of the MTJ stack.
 7. The circuit of claim 4, further comprising a second metallization layer including a second plurality of conducting lines, wherein the second metallization layer is above the free layer of the MTJ stack.
 8. The circuit of claim 7, further comprising a second interface layer between the second metallization layer and the free layer of the MTJ stack.
 9. The circuit of claim 8, wherein the second interface layer is divided by the dielectric region into a first part in the first bit cell and a second part in the second bit cell.
 10. The circuit of claim 4, further comprising: a first metallization layer including a first plurality of conducting lines, wherein the first metallization layer is below the bottom electrode of the MTJ stack; and a second metallization layer including a second plurality of conducting lines, wherein the second metallization layer is above the free layer of the MTJ stack.
 11. The circuit of claim 10, further comprising: a first interface layer between the first metallization layer and the bottom electrode of the MTJ stack; and a second interface layer between the second metallization layer and the free layer of the MTJ stack.
 12. The circuit of claim 11, wherein the second interface layer is divided by the dielectric region into a first part in the first bit cell and a second part in the second bit cell.
 13. The circuit of claim 10, wherein the first metallization layer comprises an M2 layer and the second metallization layer comprises an M3 layer.
 14. The circuit of claim 10 wherein: the first plurality of conducting lines comprises a first word line and a second word line; and the second plurality of conducting lines comprises a first bit line and a second bit line.
 15. The circuit of claim 14, wherein: the first bit cell is energizable through the first word line and the first bit line; and the second bit cell is energizable through the second word line and the second bit line.
 16. The circuit of claim 4, wherein the tunnel layer of the MTJ stack extends continuously between the first bit cell and the second bit cell.
 17. The circuit of claim 4, wherein the tunnel layer of the MTJ stack comprises a tunnel oxide layer.
 18. The circuit of claim 4, wherein the bottom electrode extends continuously between the first bit cell and the second bit cell.
 19. A circuit including a first bit cell and a second bit cell, wherein the circuit comprises: a magnetic tunnel junction (“MTJ”) stack, wherein the MTJ stack comprises: a bottom electrode; a fixed layer above the bottom electrode; a free layer above the fixed layer; and a tunnel layer between the fixed layer and the free layer; wherein the free layer is divided by a dielectric region into a first part in the first bit cell and a second part in the second bit cell, and wherein the fixed layer extends continuously between the first bit cell and the second bit cell; a first metallization layer including a first plurality of conducting lines, wherein the first metallization layer is below the bottom electrode of the MTJ stack; a second metallization layer including a second plurality of conducting lines, wherein the second metallization layer is above the free layer of the MTJ stack; a first interface layer between the first metallization layer and the bottom electrode of the MTJ stack; and a second interface layer between the second metallization layer and the free layer of the MTJ stack.
 20. The circuit of claim 19, wherein the second interface layer is divided by the dielectric region into a first part in the first bit cell and a second part in the second bit cell.
 21. The circuit of claim 19, wherein the first metallization layer comprises an M2 layer and the second metallization layer comprises an M3 layer.
 22. The circuit of claim 19, wherein the tunnel layer of the MTJ stack extends continuously between the first bit cell and the second bit cell.
 23. The circuit of claim 19, wherein the bottom electrode extends continuously between the first bit cell and the second bit cell. 